Principal Design Verification Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Microsoft is hiring a Principal Design Verification Engineer to join the AI Silicon Engineering team. This role involves creating complex verification environments and tests using UVM/SystemVerilog and C++ for pre-silicon functional verification of AI accelerators. You will collaborate with cross-disciplinary teams and adopt latest AI methodology for verification.
Responsibilities
- Creation of complex verification environments and tests using UVM/SystemVerilog and C++, for pre-silicon functional verification at the block, chip and system level, reference modeling and post-silicon validation.
- Interact with architects and design engineers to create verification plans covering strategy, test environments & tests, and verification requirements for IP/SS/SOC level verification.
- Create and drive test-plans and test development to provide complete features coverage.
- Adoption of latest AI methodology using agentic DV workflows such as Co-Pilot.
- Develop and implement technical solutions to complex quality and design challenges.
- Develop verification components like scoreboards, sequences, constraints, assertions and functional coverage.
- Triage and debug testbench, simulation, and emulation fails.
- Develop Makefiles and scripts for scalable and efficient verification.
- Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment.
- Collaborate with teams across sites and geographies.
Requirements
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
- OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
- OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
- OR equivalent experience.
- Ability to meet Microsoft, customer and/or government security screening requirements.
- Microsoft Cloud Background Check required.
Desired Qualifications
- BS/MS in Electrical, Computer or Software Engineering.
- 9+ years of experience in creating simulation environments, developing tests, and debugging for multiple silicon IP's or systems.
- 5+ years’ industry experience of chip and/or computer architecture.
- 5+ years industry experience in Verilog or VHDL, C/C++, and scripting language such as Python, Ruby or Perl.
- CPU or Graphics core verification.
- SERDES/Mixed Signal verification.
- In depth knowledge of verification principles, testbenches, stimulus generation, System Verilog, UVM, and coverage closure.
- Experience with hardware emulation or FPGAs.
- Design experience or ability to write synthesizable code.
- Software development experience.
Benefits
- The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year.
- For San Francisco Bay area and New York City metropolitan area, the base pay range is USD $188,000 - $304,200 per year.
- Certain roles may be eligible for benefits and other compensation.
#AI accelerators#SoC Design Verification#Silicon Engineering#Hardware Engineering#UVM/SystemVerilog#C++#pre-silicon functional verification#post-silicon validation#Agile development
Company
Microsoft
Job Posted
4 weeks ago
Employment Type
Full Time
WorkMode
Hybrid
Experience Level
Senior
Locations
United States
Qualification
Doctoral, Master, Bachelor
Applicants
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