Design Technology Co-Optimization Engineer, Google Cloud
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
Google Cloud seeks a Design Technology Co-Optimization Engineer in Bengaluru, India, for a mid-senior level position. The role involves bridging process technology and product architecture to define next-generation data center silicon, focusing on evaluating advanced logic nodes and transistor architectures. Requires a Bachelor's degree in a related field, 5 years of physical design experience, and scripting skills.
Responsibilities
- Execute high-fidelity Place and Route (P and R) experiments to evaluate the PPA impact of advanced process features, library architectures, and design rule variations on data center-class IP.
- Drive Design Technology Co-Optimization (DTCO) by collaborating with foundries and internal technology teams to define optimal metal stacks, track heights, and scaling boosters (e.g., backside power delivery, buried power rails).
- Quantify process entitlement through systematic benchmarking of logic and memory macros, identifying bottlenecks in power density and timing closure for next-generation nodes.
- Develop automated physical design methodologies and flows to accelerate technology pathfinding and enable rapid "what-if" analysis of emerging transistor architectures.
- Influence System Technology Co-Optimization (STCO) by partnering with Hardware Architects and Circuit Designers to translate process-level innovations into system-level performance gains.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience in Physical Design (e.g., Register-Transfer Level- to-Graphic Database System (RTL-to-GDS)) or technology development focusing on advanced nodes (e.g., 7nm, 5nm, or below).
- Experience with scripting and automation using Tcl, Python or Perl
Desired Qualifications
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with Complementary Metal-Oxide-Semiconductor (CMOS) device physics, FinFET/nanosheet architectures, and the impact of layout parasitics on PPA.
- Experience in DTCO, including standard cell library characterization, metal stack optimization, and evaluation of scaling boosters (e.g., backside power delivery).
- Experience using industry standard tools for synthesis, place and route, static timing analysis, transistor level design in advanced finfet technology nodes, including SPICE simulations.
- Experience working with major foundry technology files (PDKs) and interpreting Design Rule Manuals (DRM) to guide physical implementation.
Benefits
- Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products.
- Contribute to the innovation behind products loved by millions worldwide.
- Shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
- Work on AI and Infrastructure, redefining what’s possible and empowering customers with breakthrough capabilities and insights.
- Drive groundbreaking innovations and develop cutting-edge AI models.
- Deliver unparalleled computing power to global services and provide essential platforms for developers.
- Opportunities to work on TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
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Company
Job Posted
2 days ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Mid-Senior
Locations
Bengaluru, India
Qualification
Bachelor
Applicants
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