ASIC Physical Design, Staff Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
Synopsys seeks a Staff Engineer for ASIC Physical Design in Ho Chi Minh City, Vietnam. This role involves driving the complete digital implementation from RTL to GDS for high-speed interface IPs at advanced process nodes (7nm, 5nm, 3nm) using Synopsys EDA tools. The ideal candidate has 5+ years of experience in physical implementation, deep IC design knowledge, and strong scripting skills.
Responsibilities
- Drive complete digital implementation from RTL to GDS for high-speed interface IPs including Serdes, DDR, HDMI, MIPI, and USB at 7nm, 5nm, and 3nm nodes
- Execute synthesis, floorplanning, power planning, clock tree synthesis, placement, routing, and physical verification using Synopsys EDA tools
- Perform static timing analysis and close timing across multiple process corners, voltages, and operating modes
- Run EMIR signoff, analyze IR drop and electromigration, and iterate on power grid design to ensure reliable silicon operation
- Build physical design methodologies and automation scripts using TCL, Python, Perl, and Make to improve efficiency across projects
- Collaborate with RTL designers, verification teams, product engineers, and customers to ensure timely delivery and resolve technical issues
- Provide technical support to customers during IP integration and debug design issues as they arise
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science
- 5+ years of hands-on experience in ASIC physical implementation, specifically RTL to GDS flows using industry-standard EDA tools
- Deep understanding of IC design fundamentals, physical implementation flows, and signoff methodologies for deep submicron designs
- Proficiency with industry-standard data formats including Verilog, GDS, LEF, DEF, SDF, LIB, UPF, CPF, and SPEF
- Strong scripting skills in TCL, Python, Perl, Unix Shell, and Make for automation and flow development
- Solid written and verbal communication skills in English for technical documentation and cross-functional collaboration
- Experience with Synopsys physical design tools such as Fusion Compiler, IC Compiler II, PrimeTime, or StarRC is a strong plus
Desired Qualifications
- Ability to look at a floorplan and immediately spot congestion hotspots or power domain issues.
- Skill in analyzing and resolving timing failures by checking constraints, reviewing clock architecture, and determining necessary changes.
- Comfort in explaining timing closure strategies to product managers and IP architects.
- Ability to write readable and maintainable automation scripts.
- Treating deadlines seriously while flagging risks early.
Benefits
- Comprehensive medical and healthcare plans
- ETO and FTO Programs
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
- Retirement plans that vary by region and country
- Competitive salaries
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Company
Synopsys Inc
Job Posted
2 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Ho Chi Minh City, Vietnam
Qualification
Bachelor, Master
Applicants
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