ASIC Design /Verification Engineer, Sr Staff
Technology, Data & Digital · Software & Web Development · Software Engineering · QA & Testing
In short
Synopsys seeks a Sr. Staff ASIC Design/Verification Engineer in Tokyo, Japan, to design and implement HBM controller IP cores for advanced SoCs. This role involves micro-architecture design, verification strategy development using SystemVerilog/UVM, leading design reviews, and mentoring junior engineers, contributing to innovations in AI, automotive, and data center applications.
Responsibilities
- Design and implementation of RTL-based HBM controller IP cores for cutting-edge SoC applications.
- Interpretation and translation of standard and product functional specifications into detailed micro-architectures.
- Making architectural and methodological judgments for both design and verification activities.
- Development of comprehensive verification strategies, including testbench architectures using SystemVerilog and UVM.
- Creation and maintenance of verification plans, item lists, coverage metrics, and checker definitions.
- Coordination and leadership of design review meetings with global teams.
- Provision of technical leadership and mentoring to junior engineers.
- Documentation of progress, generation of reports with verification metrics, and ensuring project milestones are met.
- 担当: 最新のSoC向けHBMコントローラIPのRTL設計・実装
- 仕様書をもとに詳細なマイクロアーキテクチャを設計
- 設計や検証の判断や方針決定、検証計画の策定、テストベンチの構築（SystemVerilog/UVM使用）
- 設計レビューをリードし、グローバルチームと連携
- 若手エンジニアの指導や、進捗・検証レポートの作成も担当
Requirements
- Extensive hands-on experience with RTL design and micro-architecture development from functional specifications.
- Proficiency in verification methodologies (UVM/VMM/OVM), SystemVerilog, and object-oriented verification techniques.
- Deep understanding of SoC/ASIC design flows, verification planning, and coverage-driven verification.
- Experience with simulation tools, Unix operating environments, and scripting languages (Perl, Python, TCL).
- Solid knowledge of protocols such as DDR, PCIE, AMBA (AXI/CHI), SD/eMMC, Ethernet, USB, and MIPI.
- Strong English communication skills and the ability to document and present technical concepts effectively.
- BSEE with 9~10+ years or MSEE with 7~12+ years of relevant experience.
- RTL設計やマイクロアーキテクチャ設計の経験
- UVM/VMM/OVMなどの検証手法やSystemVerilogの知識
- SoC/ASIC設計フローや検証計画、カバレッジ重視の検証経験
- シミュレーションツール、Unix環境、スクリプト言語（Perl, Python, TCL）
- DDR、PCIE、AXI/CHI、SD/eMMC、Ethernet、USB、MIPIなどのプロトコル知識
- 英語でのコミュニケーション能力
- BSEE（9年以上）またはMSEE（7年以上）の実務経験
Desired Qualifications
- Advantageous: Experience with formal verification, firmware/embedded software, C/C++, and functional safety standards (ISO26262, FMEDA).
- フォーマル検証、ファームウェア・組込みソフト、C/C++、機能安全（ISO26262, FMEDA）経験
Benefits
- Comprehensive medical and healthcare plans that work for you and your family.
- In addition to company holidays, we have ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
- Save for your future with our retirement plans that vary by region and country.
- Competitive salaries.
- Competitive salaries.
#ASIC Design#Verification Engineer#RTL#IP Core Development#HBM#SoC#SystemVerilog#UVM#Semiconductor
Company
Synopsys Inc
Job Posted
2 days ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Tokyo, Japan
Qualification
Bachelor
Applicants
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