Sr Engineer - Physical Design
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
Synopsys is seeking a Sr. Engineer for Physical Design in Hyderabad, India, to work on cutting-edge semiconductor solutions. The role involves owning physical design implementation from floorplanning through tapeout on advanced nodes, driving synthesis, place and route, timing closure, and physical verification using industry-standard tools. The ideal candidate has multiple tapeouts in 5nm or below and expertise in FinFET technology.
Responsibilities
- Own physical design implementation of UCIe PHY blocks and testchips from floorplanning through tapeout on 5nm and more advanced nodes
- Drive synthesis, place and route, timing closure, and physical verification using DC, PT, ICC2/FC, and ICV across multiple concurrent projects
- Work directly with verification, DFT, and IP integration teams to resolve design issues, close timing, and meet PPA targets without slipping the schedule
- Lead design reviews, present tradeoff analyses, and make real-time decisions on floorplan changes, clock tree strategies, and signoff waivers
- Pilot new physical design flows and advanced node methodologies, then document what worked and what did not for the rest of the team
- Mentor junior engineers on timing closure techniques, physical verification strategies, and how to navigate the ICC2 toolchain effectively
- Interface with foundry partners and customer engineering teams to resolve technology file issues, DRC/LVS challenges, and silicon bring-up questions
Requirements
- 2-4 years of hands-on experience in ASIC physical design, with demonstrated expertise in synthesis, place and route, timing closure, and physical verification
- Multiple tapeouts and signoffs in 5nm or more advanced process nodes, you have taken designs all the way to GDS and dealt with the messiness that comes with it
- Proficiency with industry-standard tools including DC, PT, ICC2/FC, and ICV, you know the commands, the flow, and the workarounds
- Proven track record working on SoC or IP tapeouts where you owned significant portions of the physical design and were accountable for signoff
- Strong understanding of FinFET technology and the physical design challenges specific to advanced nodes, including multi-patterning, electromigration, and IR drop at scale
Desired Qualifications
- Experience with DFT insertion, scan chain routing, and ATPG is a strong plus, especially if you have debugged DFT-related timing or physical issues
- Exposure to UCIe, SerDes, or high-speed interface IP is valuable but not required, we care more about your physical design depth and ability to learn quickly
Benefits
- Comprehensive medical and healthcare plans
- ETO and FTO Programs
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
- Retirement Plans
- Competitive salaries
#Hardware Engineering#Physical Design#Semiconductor Solutions#Chip Architecture#Circuit Design#Verification#ASIC#RTL#GDS#Floorplanning#Timing Closure#ICC2#DC#PT#FC#ICV#PPA#DFT#FinFET#Electromigration#IR Drop#Scan Chain Routing#ATPG#UCIe#SerDes
Company
Synopsys Inc
Job Posted
1 month ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Mid-Senior
Locations
Hyderabad, India
Applicants
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