SoC DFT Technical Manager, Google Cloud
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
As a SoC DFT Technical Manager at Google Cloud in Bengaluru, you will lead the development of cutting-edge TPU technology for AI/ML applications. You will define comprehensive DFT architectures, manage the entire DFT lifecycle, and deploy next-generation methodologies to maximize test coverage and minimize test time. This role requires extensive experience in SoC DFT, people management, and collaboration with cross-functional teams.
Responsibilities
- Define and document the comprehensive DFT architecture for multi-core SoCs, including strategies for hierarchical scan compression, Memory BIST (MBIST), Functional BISTs, Analog components, Logic BIST, high-speed I/O loopback, and JTAG/IEEE 1149.1/1500/1687/1838 networks.
- Lead the complete DFT lifecycle from RTL planning to pattern handoff, owning the schedule, resource allocation, and milestone tracking to ensure zero-defect delivery.
- Deploy next-generation DFT methodologies and automation flows to maximize test coverage, while minimizing test time, pattern count, and silicon area overhead.
- Collaborate with post silicon team, Physical Design and Power Architects.
- Support the post-silicon phase to achieve final Production Release Qualification (PRQ).
- Mentor senior technical staff, drive vendor EDA tool selection/qualification, and act as the primary technical liaison for DFT matters with stakeholders.
Requirements
- Bachelor's degree in Electrical, Computer Engineering or equivalent practical experience.
- 10 years of experience in SoC DFT architecture and design.
- 10 years of experience in DFT protocols including Scan Compression, MBIST, LBIST, JTAG (IEEE 1149.1), and iJTAG (IEEE 1687).
- 10 years of experience with industry-standard EDA tools such as Siemens Tessent, Synopsys TestMAX/SMS, or Cadence Modus.
- 4 years of people management experience developing employees and leading multiple SoC projects from RTL architecture through to post-silicon validation.
- Experience in Tcl, Python, or Perl for developing automation flows.
Desired Qualifications
- PhD in Electrical Engineering with a focus on VLSI testing, fault tolerance, or reliability.
- Experience with advanced technology nodes (5nm/3nm), 2.5D/3D-IC packaging, or high-speed I/O (SerDes/DDR) testing methodologies.
- Experience managing global technical teams and driving vendor engagement.
- Ability to drive cross-functional timing closure, power analysis, and IR-drop mitigation for high-frequency designs.
Benefits
- Opportunity to shape the future of AI/ML hardware acceleration.
- Drive cutting-edge TPU technology.
- Develop custom silicon solutions.
- Contribute to innovation behind products loved by millions worldwide.
- Leverage design and verification expertise to verify complex digital designs.
- Work on a team that redefines what's possible in AI and Infrastructure.
- Empower Google customers with breakthrough capabilities and insights.
- Deliver AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
#SoC#DFT#Technical Manager#Google Cloud#AI/ML#TPU#Hardware Acceleration#Silicon#RTL#Verification#VLSI
Company
Job Posted
1 month ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Executive
Locations
Bengaluru, India
Qualification
Bachelor
Applicants
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