Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet)
Technology, Data & Digital · Software & Web Development · Software Engineering · QA & Testing
In short
Synopsys is seeking a Senior Staff Interface IP Verification Engineer in Bengaluru, India. This role involves end-to-end verification of Interface IP blocks like PCIe, CXL, DDR, and Ethernet, requiring deep expertise in SystemVerilog and UVM. The engineer will own the verification strategy, develop test plans, and debug complex issues, contributing to the quality of IP used in AI platforms, cloud infrastructure, and automotive systems.
Responsibilities
- Own end-to-end verification of Interface IP blocks including PCIe, CXL, DDR, and Ethernet, from architecture review through silicon signoff
- Build and evolve UVM-based verification environments that are reusable across product lines and scalable for future protocol generations
- Define verification strategies and test plans that account for protocol compliance, performance corner cases, and system-level integration scenarios
- Develop constrained-random, coverage-driven test scenarios using SystemVerilog and UVM, targeting functional coverage closure and signoff quality
- Debug complex multi-layer issues spanning RTL logic, protocol state machines, timing, and testbench infrastructure using VCS or equivalent simulators
- Collaborate with architecture, design, firmware, and systems teams to identify and resolve issues early in the development cycle
- Mentor verification engineers on UVM methodology, coverage analysis, debugging techniques, and verification best practices
Requirements
- Bachelor's or Master's in Electrical Engineering or Computer Engineering with 8+ years of hands-on ASIC or SoC verification experience
- Deep expertise in SystemVerilog and UVM methodology, with a track record of building scalable verification environments from the ground up
- Strong protocol knowledge in at least one of PCIe, CXL, DDR, or Ethernet, with the ability to read specs and translate them into verification requirements
- Proven experience developing constrained-random and coverage-driven verification solutions that achieve functional signoff
- Solid debugging skills across RTL, verification infrastructure, and protocol compliance, with experience using industry-standard simulators like VCS or ModelSim
Desired Qualifications
- Experience with verification IP development, assertion-based verification, or formal methods is a strong plus
- Knowledge of modern SoC architectures and high-speed communication interfaces is a plus
Benefits
- Competitive salaries
- Comprehensive medical and healthcare plans
- ETO and FTO Programs
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
- Purchase Synopsys common stock at a 15% discount
- Retirement Plans
#verification#interface ip#pre-silicon#pcie#cxl#ddr#ethernet#asic#soc#uvm#systemverilog#engineering
Company
Synopsys Inc
Job Posted
3 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Bengaluru, India
Qualification
Bachelor, Master
Applicants
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