Senior RTL Design Lead
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
We are looking for a Senior RTL Design Lead with 5-7 years of experience in RTL design using Verilog and VHDL for ASIC/SoC development. The role involves full chip RTL integration, synthesis, timing analysis, and leading a team of junior engineers. This is an on-site position based in Bangalore, India.
Responsibilities
- Utilize advanced RTL design techniques and tools like Verilog and VHDL to create efficient and optimized hardware designs.
- Lead and mentor a team of RTL designers, providing technical guidance and ensuring high-quality design solutions.
- Present and articulate design concepts, strategies, and solutions to stakeholders.
- Conduct regular reviews of design processes and methodologies, integrating industry trends and emerging technologies.
Requirements
- 5 to 7 years of experience is mandatory.
- Experience in Full chip RTL integration is preferred.
- Experience with ASIC/SoC development flow including synthesis/timing constraints development, Static Timing Analysis closure, resolving P&R congestion issues.
- Experience in RTL Synthesis.
- Scripting experience.
- Experience integrating IP's like PCIe, USB, Ethernet etc.
- Should be able to lead a team of 2 to 3 Entry Level engineers.
- Advanced proficiency in RTL design using Verilog and VHDL.
- Solid knowledge of digital design principles and methodologies.
- Familiarity with simulation tools such as Modelsim and synthesis tools like Synopsys Design Compiler.
- Strong understanding of design verification processes and tools, including UVM and SystemVerilog.
Desired Qualifications
- Certification in RTL Design or equivalent (Optional but Valuable).
Benefits
- Supercharge your potential.
- Find your career.
- Find your spark.
- A place that knows that helping its customers stay on top starts by putting its people first.
- Global technology company.
- Working with clients across all major verticals.
- Consolidated revenues as of 12 months ending June 2026 totaled $14.8 billion.
#RTL Design#Hardware Design#ASIC/SoC#Synthesis#STA#Team Lead