Senior DFT Design/Micro architect Engineer, Google Cloud
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
Google Cloud is seeking a Senior DFT Design/Micro architect Engineer in Bengaluru, India to shape the future of AI/ML hardware acceleration with TPU technology. This role involves defining, designing, and analyzing DFT implementation and flows for large-scale computing infrastructure.
Responsibilities
- Develop DFT strategy and architecture (e.g., hierarchical DFT, DFT for High speed iOs, Analog DFT).
- Develop and drive die level DFT validation strategy and Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high-test quality.
- Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.
- Document DFT architecture, test sequences, and boot-up sequences associated with test pins.
- Generate and deliver the production and debug patterns to Post Silicon engineering team and run diagnosis for post silicon supports.
Requirements
- Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
- 8 years of experience in the implementation and validation of DFT technologies.
- Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion.
- Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.
- Experience in leading DFT activities throughout an ASIC development flow.
Desired Qualifications
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.
- Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and DFT for Multi die SoCs).
- Experience in fault modeling.
- Experience in SoC cycles, silicon bringup, and silicon debug activities.
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