Principal Physical Design Methodology Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Synopsys is seeking a Principal Physical Design Methodology Engineer with 10+ years of ASIC digital implementation experience. You will lead the RTL-to-GDSII implementation flow using Synopsys tools, focusing on advanced nodes. The role involves defining and optimizing flows, scripting automation, and mentoring global teams to ensure high PPA outcomes for Interface IP products.
Responsibilities
- Lead the digital methodology engineering effort for Interface IP, defining and maintaining the complete RTL-to-GDSII implementation flow using Fusion Compiler, PrimeTime, PrimePower, and related Synopsys toolchains.
- Build, test, and deploy synthesis and place-and-route methodologies for high-speed IP cores and subsystems targeting advanced nodes (5nm, 3nm, and beyond).
- Evaluate and optimize design-for-test insertion, timing closure, power optimization, and EM/IR analysis workflows across multiple IP development teams.
- Develop automation scripts, reference flows, and documentation that design teams can actually use without calling you every time something breaks.
- Act as the technical bridge between EDA tool development teams and IP design teams, translating tool capabilities into usable methodology and feeding real-world design challenges back to tool teams.
- Mentor engineers across global teams on digital implementation best practices, timing closure strategies, and physical design tradeoffs.
- Drive continuous improvement of design processes by identifying bottlenecks, proposing solutions, and measuring impact on PPA and schedule.
Requirements
- Bachelor's or Master's in Electrical Engineering or Computer Engineering with 10+ years of hands-on ASIC digital implementation experience.
- Deep expertise with Fusion Compiler or equivalent industry synthesis and place-and-route tools (ICC2, Innovus), including advanced features like multi-mode multi-corner optimization, clock tree synthesis, and physical synthesis.
- Proven track record developing or supporting high-speed digital IP cores or SoCs, ideally in SerDes, memory controllers, or similar high-performance designs.
- Strong understanding of the full ASIC physical design flow including IP deliverables, memory compilers, standard cell libraries, and process design kits.
- Solid scripting skills in Tcl and Python for flow automation, analysis, and reporting.
Desired Qualifications
- Experience with Synopsys timing and power analysis tools like PrimeTime, PrimePower, RLTA, or CoreTools is a strong plus.
- Familiarity with high-speed interface protocols such as PCIe, DDR, USB, Ethernet, HDMI, MIPI, or DisplayPort is a strong plus.
Benefits
- Comprehensive medical and healthcare plans that work for you and your family.
- In addition to company holidays, we have ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
- Save for your future with our retirement plans that vary by region and country.
- Competitive salaries.
- Total rewards include both monetary and non-monetary offerings.
#Engineering#Electronic Design Automation#EDA#Chip Design#Verification#Manufacturing#AI/ML#GenAI#Cloud#Semiconductors#ASIC#Digital IP#PPA#Clock#Power#Area#Fusion Compiler#ICC2#Tcl#Python#RTL-to-GDSII#SerDes#Memory Controllers#PrimeTime#PrimePower#RLTA#CoreTools#PCIe#DDR#USB#Ethernet#HDMI#MIPI#DisplayPort#Physical Design Methodology
Company
Synopsys Inc
Job Posted
3 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Markham, Canada
Qualification
Bachelor, Master
Applicants
Be an early applicant