The Job

Principal ASIC Verification Engineer - DDR/LPDDR

Technology, Data & Digital · Software & Web Development · Software Engineering · QA & Testing

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In short

Synopsys is looking for a Principal ASIC Verification Engineer in Bengaluru to lead verification teams, build SystemVerilog/UVM environments for DDR/LPDDR IP cores, and ensure quality. Requires 8+ years of experience and a Bachelor's or Master's in Electrical Engineering or related field.

Responsibilities

  • Lead a team of verification engineers through full IP verification cycles, from test plan definition through coverage closure and signoff
  • Build and evolve SystemVerilog/UVM verification environments for DesignWare synthesizable IP cores, ensuring they scale across multiple product generations
  • Define test plans that cover corner cases, protocol compliance, and system-level interactions, then review and guide implementation across the team
  • Write and debug complex testbenches, checkers, and assertions for serial interface protocols and memory controllers, including DDR and LPDDR where applicable
  • Extract, analyze, and drive functional coverage and code coverage metrics to closure, identifying gaps and adjusting strategy in real time
  • Collaborate directly with RTL designers, digital architects, and circuit teams to align verification scope with design intent and catch issues early
  • Manage regression infrastructure and work with the infra team to keep verification cycles efficient and reliable

Requirements

  • Bachelor's or Master's in Electrical Engineering or Electronics and Communication Engineering with 8+ years of hands-on verification experience
  • Proven track record leading verification teams through IP project delivery, including planning, execution, and signoff
  • Strong experience developing SystemVerilog/UVM testbenches from scratch and evolving them as designs grow
  • Deep expertise writing test plans, implementing checkers, and building assertions that catch real bugs
  • Proficiency extracting and interpreting functional coverage and code coverage, and using those metrics to drive verification closure
  • Experience verifying serial interface protocols and working through IP design and verification processes
  • Demonstrated ability to own end-to-end verification deliverables, including metric closure and formal review signoff

Desired Qualifications

  • Knowledge of DDR or LPDDR protocols is a strong plus
  • Experience with AI-assisted verification tools is a plus
  • You understand that verification is not about writing tests, it is about building an environment where the right bugs cannot hide
  • You understand when to step in, when to let someone struggle productively, and when to rewrite the testbench architecture because the current one will not scale
  • You have worked with RTL designers who swear their code is clean and architects who change the spec on Thursday, and you have learned to build verification strategies that survive both
  • Memory protocols like DDR or LPDDR do not intimidate you
  • Serial interfaces, complex checkers, SystemVerilog assertions that actually mean something, these are tools you reach for without thinking
  • You care about functional coverage because it tells you what you have not tested yet, not because it is a metric someone asked for
  • You can explain a coverage hole to an architect in two sentences and walk out with a plan to close it
  • You debug by hypothesis, not by adding print statements until something makes sense
  • When a testbench is too slow or too brittle, you refactor it instead of working around it
  • You give feedback that makes engineers better, not just feedback that makes the code pass
  • You work across time zones and teams without losing context or creating confusion downstream
  • You know when to push back on a design decision and when to adjust the verification plan to match reality

Benefits

  • Competitive salaries
  • Comprehensive medical and healthcare plans that work for you and your family
  • ETO and FTO Programs
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
  • Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
  • Retirement plans that vary by region and country
#DDR#LPDDR#ASIC#Verification
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Company

Synopsys Inc

Job Posted

1 week ago

Employment Type

Full Time

WorkMode

On Site

Experience Level

Senior

Locations

Bengaluru, India

Qualification

Bachelor, Master

Applicants

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