Physical Design Engineer (Engineer up to Principal Level)
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
Qualcomm is seeking experienced Physical Design Engineers for their ASIC implementation team. Responsibilities include floorplanning, place and route, timing closure, and physical verification for advanced SoCs. Multiple career levels are available, from Engineer to Principal Engineer.
Responsibilities
- Support implementation and physical design closure of ASIC and SoC blocks.
- Execute floorplanning, placement, CTS, routing, timing analysis, and physical verification tasks under technical guidance.
- Assist in identifying and resolving timing, congestion, power, and physical implementation challenges.
- Develop scripts and automation solutions to improve design productivity.
- Collaborate with cross-functional teams to support successful project execution.
- Independently own physical implementation and signoff for complex design blocks.
- Drive timing closure, power optimization, signal integrity analysis, and design convergence across multiple operating modes and corners.
- Develop and improve implementation methodologies and automation flows.
- Analyze and resolve complex physical design issues impacting schedule, quality, or performance targets.
- Mentor junior engineers and contribute to technical best practices.
- Lead physical design execution for large subsystems or critical SoC partitions.
- Define implementation strategies to achieve aggressive power, performance, area, and schedule objectives.
- Drive cross-functional technical alignment among Design, DFT, CAD, Verification, and Product Engineering teams.
- Develop scalable methodologies, flow improvements, and automation solutions adopted across projects.
- Act as a technical subject matter expert in advanced physical implementation and design closure.
- Lead implementation and signoff of highly complex subsystems and full-chip partitions.
- Drive technical decisions impacting multiple products, programs, or business-critical deliverables.
- Provide technical leadership across multiple project teams and mentor Staff and Senior Engineers.
- Partner with architecture, design, and CAD teams to solve complex power, performance, area, and scalability challenges.
- Influence implementation strategy, design planning, technology adoption, and execution across multiple tapeouts.
- Recognized as a subject matter expert in physical design and design closure.
- Provide strategic technical leadership across multiple SoC programs and technology initiatives.
- Define and influence organizational physical design methodologies, implementation roadmaps, and best practices.
- Lead chip-level implementation, signoff, and design closure activities for highly complex products.
- Drive technology adoption, methodology innovation, and engineering excellence across teams.
- Mentor senior technical talent and serve as a recognized expert within Qualcomm's ASIC organization.
- Influence architecture, implementation strategy, and long-term execution plans across product portfolios.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field and relevant experience in ASIC design, implementation, verification, validation, integration, or related engineering disciplines.
- Experience with digital ASIC physical implementation methodologies.
- Understanding of power, performance, area, timing, and physical design tradeoffs.
- Experience working in Linux/Unix environments.
- Programming or scripting experience utilizing Python, Tcl, Perl, Shell, or similar languages.
- Strong analytical, problem-solving, and debugging skills.
- Experience with complete Physical Design Flow from synthesis through tapeout.
- Physical design expertise including floorplanning, power planning, placement, CTS, routing, timing optimization, and closure
- Experience using Cadence Innovus and/or Synopsys Fusion Compiler.
- Static Timing Analysis and timing closure experience using Synopsys PrimeTime.
- Knowledge of MMMC implementation methodologies and advanced-node design closure.
- Experience with DFT-aware implementation and functional timing constraints.
- Experience with RC extraction, signal integrity analysis, cross-talk analysis, ECO implementation, and formal verification.
- Experience with low-power implementation techniques, UPF methodologies, and power domain analysis.
- Strong communication, collaboration, and technical leadership capabilities.
Desired Qualifications
- Candidates may be considered for Engineer, Senior Engineer, Staff Engineer, or Principal Engineer opportunities depending on experience and demonstrated technical leadership.
- Expertise in one or more of the following areas: Physical Design & Implementation, ASIC Place & Route, Floorplanning, Power Planning, Clock Tree Synthesis (CTS), Static Timing Analysis (STA), MMMC Timing Closure, Signal Integrity Analysis, EM/IR Analysis, Physical Verification, DFT Implementation, Low Power Design Methodologies, Design Automation & Scripting, SoC Integration, Advanced Process Nodes, Methodology Development.
Benefits
- Opportunities for annual incentive compensation, stock awards, health and wellness programs, retirement benefits, paid time off, and professional development opportunities.
- Competitive annual discretionary bonus program and opportunity for annual RSU grants.
- Highly competitive benefits package designed to support your success at work, at home, and at play.
#ASIC#Physical Design#SoC#Chip Design#Semiconductor
Company
Qualcomm
Job Posted
2 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Mid-Senior
Locations
San Diego, United States of America
Santa Clara, United States of America
Austin, United States of America
Qualification
Bachelor
Applicants
Be an early applicant