Digital ASIC Design Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
Qualcomm is seeking a Digital ASIC Design Engineer in San Diego, California, to define, model, design, optimize, and verify IP for high-performance ASICs. The role involves RTL design, scripting, and working on cutting-edge products for mobile, automotive, compute, AI, and XR applications.
Responsibilities
- Define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development.
- Oversee definition, design, verification, and documentation for ASIC development.
- Determine architecture design, logic design, and system simulation.
- Uses tools/applications to execute the architecture and design of SOC according to design protocol provided.
- Resolves architecture, design, or verification problems by applying sound ASIC engineering practices.
- Executes the design and supports verification efforts of ASICs, SoC, and IP cores or own specific assigned part of a block.
- Focus on clock/power related features.
- Participate in the design and analyses of IPs.
- Identify areas for flow and process improvements.
- Feedback silicon learnings to improve design methodology, IP, SoC design.
Requirements
- Bachelor's degree in Science, Engineering, or related field.
- RTL design experience with Verilog/System Verilog or VHDL.
- Proficiency in any automation/scripting language such as Python/Perl.
Desired Qualifications
- Master's degree in Electrical Engineering, Computer Science, or Computer Engineering.
- 6+ months of relevant experience in ASIC design, scripting, architecture.
- Specific experience in clock design of ASIC/SOC.
Benefits
- Competitive annual discretionary bonus program.
- Opportunity for annual RSU grants.
- Highly competitive benefits package designed to support your success at work, at home, and at play.
- Equal opportunity employer, committed to providing an accessible process for individuals with disabilities.
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