Design Verification Sr Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering · QA & Testing
In short
Synopsys is seeking a Design Verification Sr Engineer in Hanoi, Vietnam, to develop and validate verification environments for high-bandwidth interface IP. This role involves writing test cases, debugging simulations, and driving coverage closure, ensuring first-pass silicon success for advanced semiconductor products.
Responsibilities
- Develop and validate verification environments for high-bandwidth interface IP from functional specifications through coverage closure
- Write test cases, assertions, and checkers in SystemVerilog to ensure comprehensive functional coverage
- Debug RTL, gate-level, and co-simulations involving real signal modeling for analog mixed-signal designs using VCS and Verdi
- Drive coverage analysis and closure across code, functional, and assertion metrics
- Participate in technical and peer reviews to ensure verification quality and process adherence
- Collaborate with design, architecture, and silicon validation teams to identify and resolve issues early
Requirements
- Bachelor's, Master's, or PhD in Electronics Engineering, Electromechanics, Telecommunications, or related field
- 2+ years of hands-on design verification experience, ideally on digital or mixed-signal IP
- Strong proficiency with SystemVerilog, UVM, and industry-standard verification methodologies
- Experience with VCS and Verdi for simulation and debug
- Solid understanding of verification planning, coverage-driven verification, and assertion-based verification
- Communicate clearly in English, whether writing a bug report, presenting coverage results, or reviewing a test plan
Desired Qualifications
- Familiarity with formal verification tools like vc_formal is a plus
- Scripting experience in Perl, TCL, or Python is a plus
- You approach debugging like a detective, following the evidence in waveforms and logs until you find the root cause, not just the symptom
- You can explain a complex verification failure to a design engineer in a way that gets them to the fix faster
- You are accountable for your work and follow through on commitments, even when a coverage gap shows up two days before a milestone
- You thrive in collaborative environments and will help a teammate debug a tricky co-simulation issue without being asked
Benefits
- Comprehensive medical and healthcare plans
- ETO and FTO Programs
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
- ESPP with a 15% discount on Synopsys common stock
- Retirement plans
- Competitive salaries
#Hardware Engineering#Semiconductor Solutions#Chip Architecture#Circuit Design#Verification#AI#5G#Cloud#IoT
Company
Synopsys Inc
Job Posted
2 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Hanoi, Vietnam
Qualification
Bachelor, Master, Doctoral
Applicants
Be an early applicant