ASIC Physical Design, Staff Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
Synopsys is looking for an experienced Staff Engineer in ASIC Physical Design to lead the full physical implementation flow from RTL to GDSII. The role involves driving timing closure, power integrity analysis, and collaborating with cross-functional teams, requiring a Bachelor's or Master's degree in Electrical Engineering and 8+ years of experience.
Responsibilities
- Lead physical implementation of high-speed interface IPs from RTL through GDSII, managing floorplanning, placement, CTS, routing, and signoff closure
- Drive timing closure using PrimeTime, resolving setup and hold violations across multiple corners and modes in advanced process nodes
- Execute power integrity analysis using RedHawk or Voltus, ensuring IR drop and electromigration compliance
- Collaborate with front-end, analog design, CAD, and product teams to integrate IP blocks and resolve interface issues
- Mentor engineers on physical design best practices, debug strategies, and methodology improvements
Requirements
- Bachelor's or Master's degree in Electrical Engineering with 8+ years of hands-on physical design experience in ASIC or IP development
- Deep expertise in the full physical design flow from RTL to GDSII, including synthesis, place and route, and physical signoff
- Proficiency with Synopsys physical design tools such as Fusion Compiler, IC Compiler II, PrimeTime, StarRC, and IC Validator
- Strong understanding of advanced node challenges including finFET effects, multi-patterning, and low-power design techniques
- Proven ability to close timing, power, and signal integrity on complex mixed-signal designs in 16nm or below
Desired Qualifications
- You make decisions with incomplete information, prioritize what matters, and adjust course when new data arrives without losing momentum
- You can explain a timing violation or power integrity issue to different audiences and tailor the message so each one understands what they need to do next
- You approach debugging methodically, isolate variables, test hypotheses, and document what you learn so the next person does not start from scratch
- You are comfortable working autonomously, figuring out what needs to happen and making it happen without waiting for direction
Benefits
- Comprehensive medical and healthcare plans that work for you and your family.
- In addition to company holidays, we have ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
- Save for your future with our retirement plans that vary by region and country.
- Competitive salaries.
#ASIC#Physical Design#Staff Engineer#Semiconductor#Hardware Engineering#Chip Architecture#Circuit Design#Verification#Silicon#RTL#GDSII#Synthesis#Place and Route#Signoff#Timing Closure#Power Integrity#Analog#CAD#Mixed-Signal IP
Company
Synopsys Inc
Job Posted
4 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Da Nang, Vietnam
Qualification
Bachelor, Master
Applicants
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