Alternate Job Titles:

• ASIC Physical Design Manager

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and accomplished leader with a deep-rooted expertise in ASIC physical design, ready to take on the challenge of managing complex chip projects from conception to tapeout. With 10-15 years of experience in the semiconductor industry, you thrive in dynamic, fast-paced environments and have successfully led teams through multiple tapeouts—at least two of which you have completed independently. Your hands-on knowledge of physical design implementation, timing closure, power optimization, and physical verification using industry-standard tools sets you apart as a technical authority in your field.

You bring a holistic understanding of the chip design flow, and your familiarity with both front-end and back-end design methodologies allows you to bridge gaps across the development cycle. Your leadership style is inclusive and motivating, fostering a culture of innovation, collaboration, and continuous learning within your team. You are adept at project and technical management, ensuring milestones are met while maintaining the highest standards of quality and efficiency. Your communication skills are exceptional, enabling you to interact effectively with cross-functional teams, foundry partners, and customers alike.

You are driven by the excitement of building next-generation embedded memory products and thrive on solving complex engineering challenges. You value diversity, are committed to mentoring others, and believe in empowering your team to achieve their best. If you are ready to make a tangible impact on cutting-edge silicon validation and design, Synopsys offers the perfect environment for your ambitions.

What You’ll Be Doing:

• Leading and mentoring a high-performing team responsible for physical design implementation and tape out of advanced ASICs and test chips.
• Driving end-to-end chip design flow, from RTL to GDSII, ensuring successful execution of multiple projects.
• Overseeing timing closure, power optimization, and physical verification using industry-standard EDA tools.
• Collaborating closely with front-end design, silicon validation, and software teams to deliver robust and efficient solutions.
• Managing project schedules, resource allocation, and risk mitigation to ensure timely and successful tape outs.
• Acting as the technical point of contact for foundry interactions and customer communications throughout the design and post-silicon support phases.
• Championing best practices in design methodology, quality assurance, and continuous process improvement.

The Impact You Will Have:

• Delivering high-quality, high-performance test chips that enable next-generation embedded memory products.
• Accelerating time-to-market for Synopsys’ customers by ensuring robust and timely tape outs.
• Enhancing the company’s technical reputation through successful project delivery and customer satisfaction.
• Driving innovation in physical design methodologies and tool flows to optimize efficiency and reliability.
• Mentoring and developing the next generation of engineering talent within the organization.
• Strengthening key partnerships with foundries and customers through proactive engagement and technical leadership.
• Contributing to the strategic direction of the Silicon Validation Design Team and influencing future product development.

What You’ll Need:

• 10-15 years of hands-on experience in ASIC physical design, with at least 5 years in a leadership role.
• Proven track record of multiple successful tape outs (minimum two completed independently).
• Expertise in physical design implementation, timing closure, power and physical verification using industry-standard EDA tools.
• Strong understanding of the complete chip design flow, from RTL to GDSII.
• Experience in project technical management, people management, and cross-functional collaboration.
• Knowledge of front-end design and RTL methodologies is a significant plus.

Who You Are:

• Inspirational leader with a collaborative and inclusive approach to team management.
• Excellent communicator, able to articulate complex technical concepts to diverse audiences.
• Analytical thinker with strong problem-solving skills and a detail-oriented mindset.
• Adaptable, proactive, and comfortable making decisions in fast-paced, evolving environments.
• Committed to continuous learning, mentoring, and fostering a culture of growth and innovation.