ASIC Digital Design, Staff Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Synopsys seeks a Staff Engineer for ASIC Digital Design in Bengaluru, India. This role involves designing and verifying high-speed Ethernet IP cores, translating specifications into micro-architectures, and driving timing closure. The ideal candidate has extensive RTL design experience with taped-out IPs and strong knowledge of various protocols.
Responsibilities
- Design and code RTL for high-speed Ethernet IP cores (100G-1.6T) with a focus on low latency and timing closure.
- Translate protocol specifications and requirements into micro-architecture and design documents for IP cores.
- Build and refine Verilog testbenches to improve functional and code coverage.
- Perform technical reviews of functional specs, micro-architecture documents, and RTL code.
- Drive timing analysis and closure using synthesis, STA, lint, CDC, and formal verification.
- Apply low power design methodologies and automotive safety requirements.
- Collaborate with verification, integration, and product teams globally to deliver production-quality IP.
Requirements
- Bachelor's in Electrical Engineering with 6+ years of ASIC/IP design experience, or Master's with 4+ years.
- Deep RTL design experience on IP cores or SoC subsystems that have taped out or shipped to customers.
- Strong knowledge of at least one protocol: AMBA (AHB, AXI, CHI), SD, eMMC, DDR, PCIe, USB, MIPI.
- Proven ability to create micro-architecture and detailed design documents from functional specs.
- Hands-on experience with Verilog/SystemVerilog, simulation tools, synthesis, STA, lint, CDC, and formal verification.
- Solid understanding of high-speed, low-latency design techniques and timing closure challenges.
- Familiarity with Perforce or similar version control systems, and scripting in Perl or shell.
Desired Qualifications
- High-speed Ethernet (100G and above) experience is a strong plus.
- Experience with datapath designs or arithmetic algorithms like FEC is a plus.
- Ability to take vague feature requests and turn them into clean, implementable designs.
- Skill in reviewing RTL and catching subtle issues.
- Ability to prioritize tasks (timing closure, coverage, reviews) effectively.
- Clear written and verbal communication for technical tradeoffs across timezones.
- Ability to push back constructively on ambiguous specs or unrealistic schedules.
- Treats documentation as an integral part of the design process.
Benefits
- Comprehensive medical and healthcare plans.
- ETO and FTO Programs in addition to company holidays.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
- ESPP: Purchase Synopsys common stock at a 15% discount.
- Retirement plans (vary by region/country).
- Competitive salaries.
- Opportunities to work on IP cores powering data center infrastructure, automotive platforms, and AI systems.
#hardware#engineering#asic#digital#design#r&d#semiconductor#ip cores#ethernet
Company
Synopsys Inc
Job Posted
1 month ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Bengaluru, India
Qualification
Bachelor, Master
Applicants
Be an early applicant