ASIC Digital Design Engineer, Staff -Sr Staff
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Synopsys is looking for an experienced ASIC Digital Design Engineer in Tokyo, Japan to contribute to architecture and micro-architecture definitions for complex protocol IP cores. The role involves designing and implementing RTL in Verilog/SystemVerilog, performing basic verification, and collaborating with implementation teams on timing and synthesis.
Responsibilities
- Understand industry standards and functional specifications, and contribute to architecture and micro-architecture definitions for complex protocol IP cores
- Design and implement RTL for digital blocks and subsystems in Verilog/SystemVerilog, balancing performance, area, power, synthesizability, and testability
- Perform basic verification and collaborate with verification teams on test planning, assertion development, functional debug, and coverage closure
- Perform RTL-level timing analysis during RTL development, and collaborate with implementation teams on STA, timing constraints, and synthesis as needed
- Support CDC/RDC/Lint signoff readiness and collaborate on design-quality closure
- Apply and explore AI-driven design tools and methodologies to improve design quality and automation
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
- 4~15+ years of experience in digital design and/or RTL development
- Hands-on experience designing and implementing synthesizable RTL in Verilog/SystemVerilog, with understanding of performance, area, power, and testability tradeoffs
- Experience with test planning, assertion development, basic verification, functional debug, and coverage closure
- Experience performing RTL-level timing analysis, with practical understanding of STA, timing constraints, and synthesis
- Experience with CDC/RDC/Lint signoff-ready design practices and design-quality closure
- Scripting experience in Python, Tcl, Perl, or Shell
- Written and oral communication skills in English and Japanese, with the ability to collaborate effectively across teams
Desired Qualifications
- Direct experience with PCIe or CXL IP design and development
- Experience with low-power design and power intent development using UPF
- Exposure to UVM or formal verification concepts
- Exposure to functional safety concepts, ISO 26262, or FMEDA
- Experience mentoring engineers or serving as a technical lead on RTL/IP development projects
- Prior experience in a global product engineering environment
Benefits
- Comprehensive medical and healthcare plans
- ETO and FTO Programs
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
- Retirement plans that vary by region and country
- Competitive salaries
#ASIC#Digital Design#RTL#IP#Semiconductor#Synopsys
Company
Synopsys Inc
Job Posted
1 month ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Tokyo, Japan
Qualification
Bachelor, Master
Applicants
Be an early applicant