Job Description

Key responsibilities:

• Layout implementation and full verification of mixed signal cells according to wafer fab design 

rules, delivering high quality, manufacturable layouts.

• All custom layout activities including cell and block level creation, edit and full verification. 

Technically execute from initiation to GDS delivery.

• Use state-of-the-art layout techniques for matching, ESD, latch-up prevention and parasitic 

reduction.

• Work within layout timelines plus any subsequent re-estimations due to design changes.
• Continuous assessment and reporting of project risks and gaps to management.
• Suggest improvements to the overall layout flows and practices. Represent the team in project 

review meetings to talk about risks and timelines to layout design.