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We are looking for a candidate with strong knowledge and experience in Signal Integrity and Power Integrity. You will be responsible for modelling package and PCB, conducting experiments, and validating modelling outcomes. Additionally, you will analyze layout files, provide practical solutions, and optimize decoupling capacitors. Knowledge of simulation tools and PDN design optimization is also required. Join us to enhance your technical capabilities and be part of our team!

Job description:

Strong knowledge in Signal Integrity and Power Integrity fundamental concepts. Strong experience in Package and PCB modelling is required. Performs Transmission line & Via modelling and carry out experiments to validate modelling outcomes and methodologies. Deep Understanding of S-parameter & its modelling concepts for Single ended and differential interfaces. Experience in simulating (FD/TD) memory interfaces for Board and Package is required (DDR4/LPDDR4) Experience in simulating (FD/TD) High Speed Serial IO interfaces for Board and Package is required (PCIe Gen3/4, SATA Gen3, USB3/3.1 and Display Interfaces etc.) Good knowledge of Power Delivery Network, impedance profile analysis, IR Drop Analysis, and time domain Analysis. Experience in extracting the PDN model of package and PCB power rails and perform decoupling capacitor optimization, Loop inductance analysis. Should be able to analyze and review the layout files related to Signal integrity and Power Integrity problems. Should be able to provide practical solutions to PCB/Package design team based on simulation results and analysis. Strong knowledge in simulation tools specifically Hspice, Sigrity (2.5D and 3D-EM Must), ADS and other tools like Ansys SIwave, HFSS 3D. PI Minimum Requirements: Solid tool skillsets (requiring minimum to no supervision) in Cadence PowerDC, PowerSI, Allegro Ansys SiWave, HFSS Synopsys HSpice Keysight ADS SimPlis/SIMetrix Good understanding of PDN mechanism S-parameter and their properties PI metrics, namely Rpath (DC R), IR drop, current density, droop, overshoot, load line (impedance profile) VR PI modeling DC, AC and Transient analysis using the tools in #1 PDN design optimization and guideline

  • To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations.
  • To be responsible for providing technical guidance or solutions
  • To develop and guide the team members in enhancing their technical capabilities and increasing productivity
  • TO ensure process compliance in the assigned module, and participate in technical discussionsorreview.
Set alert for similar jobsTechnical Lead role in Bangalore Urban, India
HCLTech Logo

Company

HCLTech

Job Posted

10 months ago

Job Type

Full-time

WorkMode

On-site

Experience Level

3-7 years

Category

IT Services and IT Consulting

Locations

Bangalore Urban, Karnataka, India

Qualification

Bachelor

Applicants

Be an early applicant

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HCLTech Logo

Technical Lead

HCLTech

Bangalore Urban, Karnataka, India

Posted: 10 months ago

We are seeking a candidate who can conceptualize and complete assigned design deliverables, prepare and own detailed verification plans, mentor and guide the team in solving technical issues, allocate and track tasks, support project management, conduct test scenarios and identify test plans, as well as coding test cases and perform functional simulation, debugging, and fixing. Join our team and contribute to our success!