Staff ASIC Digital Verification Design Engineer

Technology, Data & Digital

In short

Synopsys is seeking an experienced Staff ASIC Digital Verification Engineer in Austin, Texas. This role involves designing and implementing verification environments, creating test plans, and mentoring junior engineers to ensure the quality of Interface IP protocols. The position requires extensive experience with SystemVerilog, UVM, and simulation tools.

Responsibilities

  • Designing and implementing verification environments to ensure the correctness of Interface IP protocols.
  • Creating and executing detailed test plans to verify complex ASIC designs.
  • Developing and maintaining verification IP and testbenches using SystemVerilog and UVM.
  • Collaborating with design and architecture teams to identify and fix bugs.
  • Performing functional coverage analysis and driving coverage closure.
  • Mentoring and guiding junior verification engineers in best practices and methodologies.

Requirements

  • 5+ years' ASIC Digital Verification Engineer with BSEE/MSEE.
  • Extensive experience in ASIC digital verification, specifically with UAL, Interface IP protocols, such as PCIe, CXL, DDR, Ethernet.
  • Proficiency in SystemVerilog and UVM methodologies.
  • Strong understanding of digital design and verification concepts.
  • Experience with simulation tools such as VCS, ModelSim, or similar.
  • Excellent problem-solving skills and attention to detail.

Desired Qualifications

  • Detail-oriented with a strong analytical mindset.
  • Excellent communicator, able to convey complex technical concepts clearly.
  • Collaborative team player who thrives in a dynamic environment.
  • Proactive and self-motivated, with a commitment to continuous learning.
  • Mentor and leader, capable of guiding and developing junior engineers.

Benefits

  • Comprehensive medical and healthcare plans.
  • ETO and FTO Programs.
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
  • ESPP (Purchase Synopsys common stock at a 15% discount).
  • Retirement Plans.
  • Competitive salaries.
  • Annual bonus, equity, and other discretionary bonuses.
  • Comprehensive health, wellness, and financial benefits.
#ASIC#Digital Verification#Design Engineer#Semiconductor#Interface IP
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Company

Synopsys Inc

Job Posted

2 weeks ago

Expires

in 3 days

Employment Type

Full Time

WorkMode

On Site

Experience Level

Senior

Locations

Austin, United States

Qualification

Bachelor, Master

Applicants

Be an early applicant