SoC Systems & Infrastructure Engineer (Design • Validation • Debug • FPGA • Emulation • Software)
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems · QA & Testing
In short
Qualcomm is seeking a highly motivated SoC Systems & Infrastructure Engineer in San Diego, CA, to work on industry-leading SoCs and development platforms. This role involves developing and enhancing solutions for SoC design, validation, debug, FPGA prototyping, and emulation environments.
Responsibilities
- Develop and enhance solutions supporting SoC design, validation, debug, FPGA prototyping, and emulation environments.
- Design, implement, validate, and debug hardware and software components used in advanced SoC development platforms.
- Perform pre-silicon and post-silicon bring-up, failure analysis, root-cause investigation, and performance characterization.
- Develop automation, infrastructure, and tooling using modern programming languages and scripting environments.
- Support debugging of low-level hardware and software issues across complex SoC platforms.
- Analyze system performance, power, functionality, reliability, and timing across multiple subsystems.
- Collaborate with global engineering teams, technology partners, and tool vendors to improve methodologies, workflows, and product quality.
- Leverage automation and AI technologies to improve engineering productivity and debug efficiency.
Requirements
- Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related technical field.
- Experience in one or more of the following areas: ASIC / SoC Design, Hardware or System Debug, Validation Engineering, FPGA Development, Emulation Platforms, CAD / EDA / Software Development.
- Strong analytical, debugging, and problem-solving skills.
- Ability to work effectively in a collaborative, cross-functional environment.
- Experience with C/C++, Python, Tcl, Perl, Linux/Embedded Linux, Software Design and Development Practices, Automation and Scripting.
- Experience with ASIC Design, SoC Architecture, Hardware Validation, Hardware Debug, Performance and Power Analysis, RTL Design, Verilog / SystemVerilog, FPGA Design.
- Experience with JTAG Debug, Git, JIRA, CI/CD Automation Flows, Simulation, Emulation, and Prototyping Tools, Linux Development Environments, Hardware and Software Debug Tools.
- Proficiency in C/C++, Python, Assembly, Linux, device drivers, and bare-metal software development.
- Deep understanding of CPU, DDR, NoC/interconnects, memory hierarchy, clock/power management, low-power modes, and performance architecture.
- Experience with simulation, emulation (RUMI/Veloce/FPGA), RTL understanding, and validation readiness.
- Hands-on experience with JTAG, logic analyzers, oscilloscopes, kernel debuggers, and silicon debug methodologies.
- Experience with Xilinx and Intel FPGA platforms, FPGA firmware development, Embedded Linux, PCIe, AXI, Ethernet, and I2C protocols, High-speed digital design, Clock domain crossing and timing closure.
- Experience with Palladium and Veloce platforms, Emulation build generation, Platform bring-up, System-level debug methodologies, Timing closure and deployment flows.
- Experience with CAD tool development, Algorithms and data structures, Emulation infrastructure, Synthesis optimization, Partitioning, Clock optimization, Compute and storage optimization.
Desired Qualifications
- Master's or PhD in Computer Engineering, Electrical Engineering, Computer Science, or related field.
- Experience with complex SoC architectures including CPUs, DSPs, GPUs, DDR, NoCs, peripherals, and interconnects.
- Experience with Linux and embedded software development.
- Familiarity with modern AI-assisted engineering workflows and automation technologies.
- Experience with AI/ML to improve validation productivity.
- Experience with PVT and marginality analysis.
- Experience with AI-assisted debug automation.
- Experience with Power characterization, Thermal analysis, Vmin/Fmax characterization, CPU/GPU/DDR/NoC analysis, Performance optimization, Low-power design methodologies.
- Experience with MBIST, ATPG, Structural testing, Yield analysis, Scan-based debug, Silicon characterization.
Benefits
- Competitive annual discretionary bonus program
- Opportunity for annual RSU grants
- Highly competitive benefits package designed to support your success at work, at home, and at play.
#SoC#Systems Engineering#Infrastructure#Design#Validation#Debug#FPGA#Emulation#Software
Company
Qualcomm
Job Posted
2 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Mid-Senior
Locations
San Diego, United States of America
Qualification
Bachelor
Applicants
Be an early applicant