Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet)
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Synopsys is seeking a Senior Staff Interface IP Verification Engineer with extensive experience in PCIe, CXL, DDR, and Ethernet protocols for pre-silicon verification. The role involves owning end-to-end verification, building UVM environments, defining strategies, and mentoring junior engineers to ensure the quality and reliability of semiconductor products.
Responsibilities
- Own end-to-end verification of Interface IP blocks including PCIe, CXL, DDR, and Ethernet, from architecture review through silicon signoff
- Build and evolve UVM-based verification environments that are reusable across product lines and scalable for future protocol generations
- Define verification strategies and test plans that account for protocol compliance, performance corner cases, and system-level integration scenarios
- Develop constrained-random, coverage-driven test scenarios using SystemVerilog and UVM, targeting functional coverage closure and signoff quality
- Debug complex multi-layer issues spanning RTL logic, protocol state machines, timing, and testbench infrastructure using VCS or equivalent simulators
- Collaborate with architecture, design, firmware, and systems teams to identify and resolve issues early in the development cycle
- Mentor verification engineers on UVM methodology, coverage analysis, debugging techniques, and verification best practices
Requirements
- Bachelor's or Master's in Electrical Engineering or Computer Engineering with 8+ years of hands-on ASIC or SoC verification experience
- Deep expertise in SystemVerilog and UVM methodology, with a track record of building scalable verification environments from the ground up
- Strong protocol knowledge in at least one of PCIe, CXL, DDR, or Ethernet, with the ability to read specs and translate them into verification requirements
- Proven experience developing constrained-random and coverage-driven verification solutions that achieve functional signoff
- Solid debugging skills across RTL, verification infrastructure, and protocol compliance, with experience using industry-standard simulators like VCS or ModelSim
Desired Qualifications
- Experience with verification IP development, assertion-based verification, or formal methods is a strong plus
- Knowledge of modern SoC architectures and high-speed communication interfaces is a plus
Benefits
- Comprehensive medical and healthcare plans
- ETO and FTO Programs
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
- Retirement plans
- Competitive salaries
#semiconductor#verification#PCIe#CXL#DDR#Ethernet#ASIC#SoC#RTL#UVM#SystemVerilog#Pre-Silicon#IP Verification
Company
Synopsys Inc
Job Posted
1 week ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Bengaluru, India
Qualification
Bachelor, Master
Applicants
Be an early applicant