Senior Silicon Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Microsoft is looking for a Senior Silicon Engineer to design and verify analog circuit components for custom SerDes interface IP. This role involves mixed-signal validation, generating timing models, and collaborating with design teams. The ideal candidate will have a strong educational background in Electrical Engineering or a related field and several years of relevant experience.
Responsibilities
- Design and verify analog circuit components for custom SerDes interface IP (e.g. PLL, Clock Distribution, Transmit and Receive Macros).
- Perform Mixed Signal Validation of blocks to validate calibration functionality end-to-end.
- Generate timing models for analog interfaces to digital blocks.
- Conduct Simulation, post-layout verification & co-ordination with layout designers and other engineers on the macro.
- Co-ordinate with designers to ensure behavioral model accuracy.
Requirements
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
- Ability to meet Microsoft, customer and/or government security screening requirements.
- Must pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
- Ability to access information controlled for export under export control regulations (e.g., ITAR, EAR, EU Dual Use Regulation).
- Successful candidate will be required to provide proof of country of citizenship or US residency/protected status for assessment of eligibility to access export-controlled information.
- Citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Desired Qualifications
- MS in Electrical Engineering or PhD in Electrical Engineering.
- 7+ years with MS EE and 5+ years with PhD in Electrical Engineering.
- Experience with deep sub-micron nodes and hands on layout optimization experience.
- Ability to review DV waveforms and debug calibration related issues.
- Experienced with behavioural modeling (System Verilog, LEC).
- Post silicon validation.
- Python, Perl & other scripting languages for post silicon validation.
- Analog Behavioural Modeling of PLL Components.
Benefits
- The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year.
- In San Francisco Bay area and New York City metropolitan area, the base pay range for this role is USD $160,200 - $261,000 per year.
- Certain roles may be eligible for benefits and other compensation.
#Silicon Engineering#Hardware Engineering#SerDes interface IP#PLL#Clock Distribution#Transmit and Receive Macros#Mixed Signal Validation#timing models#analog interfaces#digital blocks#Simulation#post-layout verification#behavioral model#analog circuit components#export control#deep sub-micron nodes#layout optimization#post silicon validation#scripting languages
Company
Microsoft
Job Posted
3 weeks ago
Employment Type
Full Time
WorkMode
Hybrid
Experience Level
Senior
Locations
Redmond, United States
Qualification
Doctoral, Master, Bachelor
Applicants
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