Senior IP Micro-architect (RTL) - Sr Lead/Staff
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Qualcomm is seeking a Senior IP Micro-architect (RTL) in Bangalore, India, to lead the definition and development of complex custom IPs from concept to silicon. The role involves hands-on technical leadership, microarchitecture development, RTL implementation, and performance optimization, with a focus on Infrastructure IPs, memory systems, and interconnect fabrics.
Responsibilities
- Drive architecture and microarchitecture definition of complex custom Infrastructure IPs.
- Develop detailed microarchitecture specifications including datapath design, control logic, packet formats, flow control, ordering rules, coherency mechanisms, and state machines.
- Lead RTL development and collaborate closely with verification, physical design, firmware, and SoC integration teams.
- Evaluate and optimize architecture trade-offs across performance, power, area, scalability, latency, and implementation complexity.
- Design and develop high-performance interconnect, memory, and protocol-centric IP solutions.
- Drive design reviews, microarchitecture reviews, and technical decision-making across multiple projects.
- Support verification planning, debug, emulation, FPGA validation, and silicon bring-up activities.
- Ensure RTL quality through lint, CDC/RDC, synthesis, and design signoff methodologies.
- Mentor junior engineers and provide technical leadership within the IP development team.
- Stay abreast of emerging technologies in AI infrastructure, scale-up fabrics, memory systems, and high-speed interconnects.
Requirements
- 8-15 years of experience in SoC/IP architecture, microarchitecture, and RTL design.
- Proven experience defining and delivering complex custom IPs from concept through production silicon.
- Strong experience in architecture and microarchitecture development of one or more of the following: Infrastructure IPs, NoC, interconnect fabrics, memory subsystem IPs, cache coherency solutions, or high-speed interface IPs.
- Strong understanding of computer architecture, SoC architecture, digital design methodologies, performance modeling and analysis, synchronization and flow control mechanisms, and high-performance data movement architectures.
- Hands-on RTL design experience using Verilog/SystemVerilog.
- Experience with design signoff methodologies including lint, CDC/RDC, synthesis, and timing closure fundamentals.
- Strong debugging, analytical, and problem-solving skills.
- Excellent verbal and written communication skills.
- Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field.
Desired Qualifications
- Minimum Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
- OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
- OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
#IP Micro-architect#RTL#Hardware Engineering#SoC#Custom IP#Protocol Design#Performance Optimization#Silicon Delivery#Infrastructure IP#NoC#PCIe#CXL#Memory Systems#Cache Coherency#UALink#ESUN#Interconnect Fabrics#Verilog#SystemVerilog#Lint#CDC/RDC#Synthesis#Timing Closure
Company
Qualcomm
Job Posted
2 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Bangalore, India
Qualification
Bachelor, Master, Doctoral
Applicants
Be an early applicant