RTL Design Sr Staff Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Synopsys is seeking an experienced RTL Design Sr Staff Engineer to design and develop high-speed mixed-signal PHY IP blocks. The role involves creating detailed micro-architecture specifications, executing RTL design from concept to tape-out, and collaborating with verification and customer support teams globally. This position is based on-site in Ho Chi Minh City, Vietnam.
Responsibilities
- Design and develop high-speed mixed-signal PHY IP blocks in SystemVerilog and Verilog as part of a cross-functional digital design team
- Author detailed micro-architecture specifications based on industry protocol standards, translating requirements into implementable design decisions
- Execute RTL design from concept through tape-out, ensuring design quality through Linting, CDC checks, and adherence to coding standards
- Collaborate with verification engineers to debug and resolve issues in RTL simulations and gate-level simulations with SDF timing annotation
- Provide technical support to customers during SoC integration, post-silicon bring-up, and field deployment
- Participate in design reviews and mentor junior engineers on RTL best practices
Requirements
- 5+ years of hands-on experience in ASIC RTL design flow, from specification through tape-out
- Strong proficiency in SystemVerilog and Verilog for complex digital design
- Experience with scripting languages such as Python, Perl, or Tcl for design automation
- Solid understanding of design quality checks including Linting, CDC analysis, and synthesis constraints
- Strong English communication skills for cross-functional collaboration and customer interaction
Desired Qualifications
- Experience with post-silicon debugging and customer support is a strong plus
- Knowledge of high-speed serial protocols, DFT techniques, or UVM verification methodologies is a plus
Benefits
- Competitive salaries
- Comprehensive medical and healthcare plans
- ETO and FTO Programs
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
- Retirement plans that vary by region and country
#ASIC#RTL Design#PHY IP#SystemVerilog#Verilog#micro-architecture#Linting#CDC#synthesis#SoC integration#post-silicon debugging#protocol standards
Company
Synopsys Inc
Job Posted
2 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Ho Chi Minh City, Vietnam
Applicants
Be an early applicant