RTL Design Engineer, Sr Lead
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Qualcomm seeks a Sr Lead RTL Design Engineer with 5+ years of ASIC/SoC front-end design experience in Bangalore, India. Responsibilities include micro-architecture definition, RTL implementation using Verilog/SystemVerilog, and quality signoff activities like Lint and CDC analysis, with a strong emphasis on collaborating with cross-functional teams for silicon delivery.
Responsibilities
- Develop detailed micro-architecture specifications.
- Design and implement synthesizable RTL using Verilog/SystemVerilog.
- Participate in design reviews and ensure design quality.
- Perform RTL quality checks including Lint and CDC/RDC analysis.
- Develop and maintain design documentation.
- Work closely with verification teams to resolve functional issues.
- Support synthesis, timing analysis, and timing closure activities.
- Develop and review SDC constraints.
- Analyze and debug issues across simulation, synthesis, and implementation stages.
- Collaborate with DFT and physical design teams for successful integration and tapeout.
Requirements
- Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field.
- 5+ years of experience in ASIC/SoC front-end design.
- Strong knowledge of digital design fundamentals.
- Hands-on expertise in RTL design using Verilog/SystemVerilog.
- Experience with micro-architecture definition and documentation.
- Experience with Lint tools (SpyGlass, Questa Lint, or equivalent).
- Experience with CDC/RDC tools (SpyGlass CDC, Questa CDC, or equivalent).
- Good understanding of clocking architectures, reset strategies, and low-power design concepts.
- Experience debugging RTL and simulation issues.
Desired Qualifications
- Experience with synthesis flows using Design Compiler, Genus, or equivalent tools.
- Experience creating and reviewing timing constraints (SDC).
- Understanding of timing analysis concepts including setup/hold, clock domain crossings, and timing closure.
- Exposure to DFT methodologies and integration.
- Knowledge of low-power design techniques (UPF/CPF).
- Experience with complex SoC/IP development and integration.
- Strong analytical and debugging skills.
- Excellent written and verbal communication.
- Ability to work independently and drive block ownership.
- Strong collaboration skills across architecture, verification, and physical design teams.
- Experience working on high-performance CPU, DSP, AI/ML, networking, multimedia, or connectivity IPs.
- Scripting knowledge in Python, Perl, or TCL for automation and flow enhancement.
Benefits
- Equal opportunity employer committed to providing an accessible process.
- Reasonable accommodations available for individuals with disabilities.
#ASIC#SoC#RTL#Hardware Engineering#Micro-architecture#Lint#CDC#RDC#Synthesis#Timing Constraints#DFT#Physical Design
Company
Qualcomm
Job Posted
3 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Bangalore, India
Qualification
Bachelor, Master, Doctoral
Applicants
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