The Job

R&D Engineering, Sr Staff Engineer (RTL Design Engineer - FPGA)

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

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In short

Synopsys is seeking a Sr. Staff Engineer for RTL Design (FPGA) in Bengaluru, India. This role involves designing and developing advanced FPGA-based prototyping solutions, leading digital design processes, and implementing complex EDA software. Requires MS/PhD with 10+ years of experience in RTL development, FPGA platforms, and scripting languages.

Responsibilities

  • Designing and developing advanced FPGA-based prototyping solutions, integrating both hardware and software components.
  • Leading the digital design process for Xilinx and Altera FPGAs, utilizing tools such as Xilinx Vivado to optimize workflows.
  • Driving all phases of the project lifecycle, including requirements gathering, development, implementation, and test case creation.
  • Developing and maintaining complex EDA (Electronic Design Automation) software for high-performance prototyping systems.
  • Implementing digital debug, verification, emulation, and prototyping strategies to ensure robust and reliable designs.
  • Creating RTL for interfaces such as USB, PCIe, DDR, and AXI, and overseeing full design flow including verification and lab bring-up.
  • Supporting and enhancing existing products and features, responding to evolving customer needs with innovative solutions.
  • Exploring and implementing new approaches to address current and future challenges, continuously learning and applying new technologies.
  • Mentoring junior engineers, providing guidance and support to foster growth and technical excellence within the team.
  • Collaborating independently and within cross-functional teams, networking with senior internal and external stakeholders.

Requirements

  • MS/PhD in Computer Science, Electrical Engineering, or related field from a reputed institute, with 10+ years of relevant experience.
  • Expertise in RTL development using Verilog or System Verilog, with a strong background in digital design principles.
  • Hands-on experience with Xilinx and Altera FPGA platforms, including familiarity with Xilinx Vivado and related tools.
  • Proficiency in developing large, complex EDA software and managing the full design flow from concept to lab bring-up.
  • Advanced problem-solving and debugging skills, especially in digital verification, emulation, and prototyping environments.
  • Experience with scripting languages such as Tcl, Python, Perl, and a solid understanding of system and CPU architecture (DMA, interrupts, etc.).
  • Exposure to embedded system development and interface protocols (USB, PCIe, DDR, AXI).

Desired Qualifications

  • Innovative thinker who embraces new challenges and technologies.
  • Strong communicator, able to articulate complex ideas to diverse audiences.
  • Collaborative leader, fostering teamwork and mentoring junior engineers.
  • Detail-oriented and committed to delivering high-quality results.
  • Adaptable, continuously learning and thriving in a dynamic environment.
  • Inclusive, valuing diversity and different perspectives within the team.

Benefits

  • Competitive salaries.
  • Comprehensive medical and healthcare plans.
  • ETO and FTO Programs.
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
  • ESPP (Purchase Synopsys common stock at a 15% discount, with a 24 month look-back).
  • Retirement Plans (vary by region and country).
#FPGA#RTL Design#EDA#Xilinx#Altera#Semiconductors#Chip Design
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Company

Synopsys Inc

Job Posted

2 weeks ago

Employment Type

Full Time

WorkMode

On Site

Experience Level

Senior

Locations

Bengaluru, India

Qualification

Master

Applicants

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