Principal Post-Silicon Applications Engineer
Construction, Engineering & Trades · Civil & Industrial Engineering · Electrical Engineering
In short
We are seeking a Principal Post-Silicon Applications Engineer with deep expertise in PCIe 6.0/7.0 silicon bring-up and debugging. You will lead root cause analysis for complex issues spanning analog, digital, and system integration, utilizing advanced lab equipment and providing on-site support to customers globally.
Responsibilities
- Provide senior-level technical support to customers during silicon bring-up and production phases for PCIe 6.0, PCIe 7.0, including on-site engagement when critical issues require direct technical presence
- Lead comprehensive root cause analysis for complex signal integrity, protocol compliance, and interoperability challenges across analog, digital, and system integration layers
- Utilize advanced laboratory instrumentation including high-bandwidth oscilloscopes, real-time spectrum analyzers, bit error rate testers, vector network analyzers, and protocol analyzers to perform precision measurements and isolate failure mechanisms at 64 GT/s and higher data rates
- Analyze and simulate Verilog/SystemVerilogRTL, collaborating with digital design and firmware teams to resolve issues involving PAM4 encoding, FLIT mode operation, and link training state machine behavior
- Drive technical engagements with customer engineering teams and system architects, translating technical findings into clear recommendations and design guidance
- Develop and refine test methodologies, debug procedures, and technical best practices for next-generation SerDes validation and customer deployment
- Travel approximately twice per year to customer locations or internal development sites for critical bring-up support and technical collaboration
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related discipline with 10+ years of hands-on experience in post-silicon validation, applications engineering, or SerDes bring-up
- Extensive expertise with PCIe 6.0 or newer standards, including PAM4 signaling, FLIT mode operation, link training protocols, and compliance testing at 64 GT/s and above
- Demonstrated proficiency using advanced laboratory equipment including high-bandwidth oscilloscopes, real-time spectrum analyzers, bit error rate testers, vector network analyzers, and protocol analyzers for signal integrity and protocol debug
- Experience analyzing and simulating Verilog or SystemVerilog RTL to diagnose digital design issues affecting silicon behavior
- Solid understanding of high-speed printed circuit board design, signal integrity principles, power delivery architectures, and system-level integration is highly valuable
- Willingness to travel approximately twice per year for on-site customer support and internal technical collaboration
Desired Qualifications
- Approach complex technical failures systematically, pursuing root cause understanding rather than symptomatic resolution
- Engage effectively with senior customer architects, present technical data and analysis clearly, and establish credibility through demonstrated expertise and professional communication
- Transition effectively between laboratory work, RTL analysis, customer interactions, and internal design reviews
- Produce clear, well-structured technical documentation and debug reports
- Take ownership of ambiguous technical challenges, define appropriate resolution paths, and coordinate with relevant stakeholders without requiring external direction
- Develop the capabilities of less experienced engineers through structured knowledge transfer
Benefits
- Comprehensive range of health, wellness, and financial benefits
- Total rewards include both monetary and non-monetary offerings
- Opportunity to work with the most advanced SerDes IP in the industry
- Enable customer tape-outs and production ramps by resolving technical blockers
- Establish Synopsys as a recognized technical authority in PCIe 6.0/7.0
- Provide real-world silicon and system-level insights to IP design, validation, and product development teams
- Reduce costly silicon re-spins by identifying and resolving subtle issues
- Develop the technical capabilities of applications and validation engineers
- Contribute to the technical roadmap for SerDes applications engineering
- Build enduring customer relationships
#Engineering#Post-Silicon#Applications Engineer#PCIe#SerDes
Company
Synopsys Inc
Job Posted
1 week ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Porto Salvo, Portugal
Qualification
Bachelor, Master
Applicants
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