PCIe System Architect/ Principal Engineer-18290
Construction, Engineering & Trades · Civil & Industrial Engineering · Mechanical Engineering
In short
Synopsys is seeking a PCIe/CXL System Architect/Principal Engineer in Sunnyvale, California. This customer-facing role involves guiding customers on SoC integration, PCIe/CXL controller IP, and system-level decisions to drive technological innovation.
Responsibilities
- Own the technical architecture engagement for PCIe/CXL controller IP with strategic customers.
- Work with customer architects and engineering teams to define suitable PCIe/CXL subsystem configurations.
- Analyze system-level trade-offs related to performance, power, reliability, validation, compliance, and interoperability.
- Translate customer platform requirements into clear feedback for Synopsys Product Management, R&D, and roadmap planning.
- Support technical closure of design wins by providing architecture guidance.
- Develop reusable technical material and customer-facing guidance.
- Train FAEs and customer teams on PCIe/CXL architecture and best practices.
Requirements
- Bachelors and/or Masters Degree in Electrical and/or Electronic Engineering, Computer Engineering or Computer Science.
- 10+ years of experience in PCIe/CXL architecture, SoC integration, silicon validation, systems engineering, applications engineering, or customer-facing technical leadership.
- Solid understanding of PCIe and/or CXL controller IP, including protocol concepts, configuration, integration, validation, compliance, or interoperability.
- Good system-level understanding of SoC integration and ability to reason through performance, power, reliability, validation, and software/firmware trade-offs.
- Experience engaging directly with customer architects, design teams, validation teams, and technical decision-makers.
- Ability to translate ambiguous customer requirements into clear technical recommendations.
- Strong technical communication skills.
Desired Qualifications
- Experience with Linux, firmware bring-up, or software-driven debug of PCIe/CXL subsystems.
- Familiarity with advanced SoC architectures used in AI, HPC, storage, networking, or compute platforms.
- Participation in PCI-SIG, CXL Consortium, or related ecosystem/standards activities.
- Knowledge of advanced topics such as coherency, virtualization, RAS, memory expansion, or CXL-based platform architectures.
Benefits
- Comprehensive range of health, wellness, and financial benefits.
- Total rewards include both monetary and non-monetary offerings.
- Annual bonus, equity, and other discretionary bonuses may be available.
- Comprehensive health, wellness, and financial benefits as part of a competitive total rewards package.
- The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education.
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