Display Synthesis Engineer, Senior
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
Qualcomm is seeking a Senior Display Synthesis Engineer in Bangalore, India. This role involves leading a team in the implementation domain for Display Sub-System, focusing on physical synthesis, timing closure, and low-power design methodologies using industry-standard tools.
Responsibilities
- Develop signoff quality constraints and power intent constraints.
- Perform synthesis, LEC, low power checks, and memory BIST insertion.
- Develop and analyze TCL scripts for designs.
- Lead a team of engineers in the implementation domain for Display Sub-System.
- Manage multiple time-critical and complex project executions.
- Improve execution efficiency and optimize for area, power, and performance.
- Grow the team technically and in size.
- Innovate and bring fresh ideas to the team.
- Work independently with design, DFT, and PD teams for netlist delivery and timing constraints validation.
- Handle ECOs and formal verification while maintaining high quality metrics.
Requirements
- Bachelor’s or master’s degree in engineering with 5+ Years of experience.
- Strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools.
- Experience with writing timing constraints for synthesis, STA, timing closure, and pipelining for performance optimization.
- Experience in all aspects of timing closure for multi-clock domain designs.
- Familiarity with MCMM synthesis and optimization.
- Good understanding of low-power design implementation using UPF.
- Experience with scripting languages such as Perl, Python, TCL.
- Experience with different power optimization flows or techniques such as clock gating.
- 3+ years of experience in Synthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation.
Desired Qualifications
- Experience with Synopsys DCG/Genus/Fusion Compiler.
- Experience with Synopsys Prime Time including constraint development for complex blocks with multiple clock domains.
- Experience with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development.
- Experience with either RTL development or Physical Design is also a plus.
- Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure.
- Should be familiar with MCMM synthesis and optimization.
- Experience with different power optimization flows or technique such as clock gating.
Benefits
- Qualcomm is an equal opportunity employer.
- Commitment to providing accessible process for individuals with disabilities.
- Reasonable accommodations to support individuals with disabilities.
- Making our workplace accessible for individuals with disabilities.
#Display#Synthesis#Engineer#Senior#Qualcomm
Company
Qualcomm
Job Posted
1 week ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Bangalore, India
Qualification
Bachelor, Master, Doctoral
Applicants
Be an early applicant