Design Verification Engineer — Memory Subsystem
Technology, Data & Digital · Software & Web Development · Software Engineering · QA & Testing
In short
Qualcomm seeks a motivated Design Verification Engineer for its memory subsystem team. Responsibilities include developing and executing verification strategies for complex digital designs like memory controllers, DDR/LPDDR/HBM interfaces, and related components. The role involves the full verification lifecycle, from planning to debugging and coverage closure, using Verilog, SystemVerilog, UVM, and assertions.
Responsibilities
- Develop verification strategies, test plans, and coverage plans for complex RTL designs.
- Build, enhance, and maintain reusable SystemVerilog/UVM and formal verification environments.
- Develop and maintain UVM components, including sequences, drivers, monitors, scoreboards, agents, environments, test configurations, and functional coverage models.
- Create and execute constrained-random, directed, error-injection, and corner-case tests.
- Write and maintain SystemVerilog Assertions for protocol, interface, timing, and functional verification.
- Verify memory-controller, PHY-interface, and memory-subsystem functionality across multiple operating modes.
- Analyze simulation failures using waveform viewers, simulation logs, transaction databases, and other debug tools.
- Perform root-cause analysis of verification failures and collaborate with RTL, architecture, modeling, and integration teams to resolve issues.
- Review RTL, microarchitecture specifications, interface definitions, and design changes for functional correctness, completeness, and verifiability.
- Support regression execution, failure triage, failure classification, and verification status reporting.
- Drive functional, code, assertion, and coverage closure.
- Collaborate with cross-functional teams, including architecture, design, physical design, firmware, modeling, and system validation teams.
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
- 3–10 years of experience in ASIC, SoC, IP, or subsystem design verification.
- Strong hands-on experience with Verilog, SystemVerilog, UVM, and SystemVerilog Assertions.
- Experience developing and debugging reusable UVM-based verification environments.
- Proficiency in developing UVM components such as sequences, drivers, monitors, scoreboards, agents, and functional coverage models.
- Experience with constrained-random verification and coverage-driven verification methodologies.
- Experience writing assertions for protocol compliance, temporal behavior, interface checking, and functional correctness.
- Strong understanding of digital design and verification fundamentals, including clocking, reset behavior, synchronous and asynchronous logic, and multi-clock-domain designs.
- Experience with simulation-based verification, waveform analysis, regression execution, and failure debug.
- Strong analytical, problem-solving, communication, and collaboration skills.
- Minimum Qualifications: Bachelor's degree and 4+ years of ASIC design, verification, validation, integration, or related work experience; OR Master's degree and 3+ years; OR PhD and 2+ years.
Desired Qualifications
- Experience verifying LPDDR, DDR, DDR PHY, HBM, custom memory interfaces.
- Familiarity with JEDEC memory specifications and memory-protocol requirements.
- Understanding of memory-controller, memory-subsystem, and PHY architecture.
- Familiarity with integrating and configuring industry-standard verification IP.
- Experience working with commercial or internally developed memory models.
- Experience with power-aware simulation using UPF.
- Knowledge of standard interfaces such as AXI, APB, AHB, DFI, or similar protocols.
- Experience with formal verification or assertion-based verification methodologies.
- Experience verifying high-performance, low-power, or multi-clock-domain designs.
- Experience with performance verification, including bandwidth, latency, throughput, efficiency, QoS, and stress testing of memory subsystems.
- Familiarity with hardware/software co-verification or system-level validation.
- Experience with memory training, initialization, refresh, power-management, frequency-switching, calibration, or error-handling scenarios.
Benefits
- Competitive annual discretionary bonus program.
- Opportunity for annual RSU grants.
- Highly competitive benefits package designed to support your success at work, at home, and at play.
#ASIC#SoC#IP#subsystem#memory#verification#RTL#UVM#SystemVerilog#LPDDR#DDR#HBM#JEDEC
Company
Qualcomm
Job Posted
2 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Mid-Senior
Locations
Santa Clara, United States of America
Qualification
Bachelor, Master, Doctoral
Applicants
Be an early applicant