ASIC Digital Design, Staff Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
Synopsys is seeking a Staff Engineer in ASIC Digital Design for their Bengaluru, India office. This role involves leading verification ownership for critical subsystem areas, including IP integration, and driving strategy and execution with a team of verification engineers. The ideal candidate has a Bachelor's or Master's degree and 8+ years of experience in ASIC/FPGA verification with expertise in SystemVerilog and UVM.
Responsibilities
- Lead verification ownership for critical Subsystem areas, driving strategy and execution alongside a team of verification engineers working on DDR, HBM, PCIe, UCIe, Ethernet, UALink, or UFS IP integration
- Define, implement, and track detailed verification test plans that map coverage goals to real silicon risk, ensuring nothing slips through
- Build and maintain Subsystem-level UVM testbenches in SystemVerilog, integrating RTL and behavioral models into a cohesive verification environment
- Write complex test cases, assertions, and checkers that catch the corner cases other teams miss, and debug simulation failures down to root cause
- Extract, analyze, and drive closure on functional coverage and code coverage metrics, working with the team to close gaps before signoff
- Manage regression suites and contribute to continuous improvement of verification flows, methodologies, and automation
- Collaborate directly with RTL designers and architects across global sites to ensure functional correctness and alignment on design intent
Requirements
- Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related technical field
- 8+ years of hands-on experience in ASIC or FPGA verification, with a track record of owning verification deliverables from planning through signoff
- Proven expertise developing SystemVerilog and UVM-based testbenches for complex ASIC designs, including experience with assertions, checkers, and constrained random stimulus
- Strong ability to define verification strategies, write rigorous test plans, and drive coverage closure using functional coverage and code coverage analysis
- Experience technically leading a verification team or mentoring engineers, with demonstrated success collaborating across design, architecture, and verification teams
- Deep understanding of verification metrics, regression management, and debugging complex simulation failures in large-scale environments
- Experience with high-speed interface protocols such as DDR, HBM, PCIe, UCIe, Ethernet, UALink, or UFS is highly desirable and will set you apart
Desired Qualifications
- You can look at a failing regression, pull up the waveform, and within an hour tell the team whether it is a testbench bug, an RTL issue, or a timing corner no one considered
- When a junior engineer brings you a stuck debug, you do not just give them the answer, you walk them through how to isolate the problem so they can solve the next one themselves
- You push back when a test plan is too shallow or a coverage model misses an important state transition, and you do it in a way that makes the team stronger, not defensive
- You stay current on verification techniques and tools, whether that is exploring AI-assisted verification flows or adopting new UVM patterns that improve reuse and debug speed
- You communicate clearly across time zones and disciplines, translating verification status into terms that architects, designers, and project leads can act on
- You take ownership seriously, if a coverage hole or test gap exists in your area, you do not wait for someone else to notice, you flag it and drive it to closure
Benefits
- Competitive salaries
- Comprehensive medical and healthcare plans that work for you and your family
- In addition to company holidays, we have ETO and FTO Programs
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
- Save for your future with our retirement plans that vary by region and country
- Total rewards include both monetary and non-monetary offerings
#ASIC#Digital Design#Staff Engineer#Hardware Engineering#Synopsys#Bengaluru#Karnataka#India#Engineering#Employee#Chip Architecture#Circuit Design#Verification#Semiconductor Solutions#Semiconductor Products#Subsystem#DDR#PCIe#UCIe#Ethernet#UALink#UFS#IP Integration#SystemVerilog#UVM#RTL#Functional Correctness#AI#Automotive#Cloud Infrastructure#EDA
Company
Synopsys Inc
Job Posted
3 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Bengaluru, India
Qualification
Bachelor, Master
Applicants
Be an early applicant